Semiconductor package having a cavity structure

ABSTRACT

A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit of the following commonlyowned U.S. provisional patent application, which is incorporated hereinby reference in its entirety: U.S. Provisional Patent Application No.61/036,470, entitled “Chip Package Structure and Manufacturing MethodsThereof,” filed on Mar. 14, 2008.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor chip packages.More particularly, this invention relates to an advanced Quad Flat NoLead (aQFN) chip package having a cavity structure and manufacturingmethods thereof.

BACKGROUND OF THE INVENTION

Semiconductor chips have become progressively more complex, driven inlarge part by the need for increasing processing power in a smaller chipsize. In response, packaging technologies have evolved, for example, toenable an increased lead density, which can reduce the footprint area ofa package mounted on a printed circuit board (PCB). Some packagingtechnologies, such as Quad Flat No Lead (QFN), may enable this increasedlead density by providing inner and outer rows of leads connected to adisposable portion of a leadframe. However, manufacturing processes forsuch leadframes may not be scalable beyond two rows of leads. As leaddensity requirements further increase, it may be desirable to usepackaging technologies that are more scalable in terms of lead density.

Moreover, it may be desirable to further reduce package size inadditional ways, such as by reducing package height. At the same time,it may be desirable to maintain sufficient mold locking of leads to apackage body, and to facilitate surface mounting of the package to aPCB. It may also be desirable to formulate a packaging process designedto meet these objectives. Current packaging solutions can meet some ofthese objectives but may not be able to meet most, or all, of theseobjectives.

It is against this background that a need arose to develop the chippackage and associated manufacturing methods described herein.

SUMMARY OF THE INVENTION

In one innovative aspect, the invention relates to a semiconductorpackage. In one embodiment, the semiconductor package includes a diepad, a plurality of leads, a semiconductor chip, and a package body. Thedie pad includes: (1) a peripheral edge region including an uppersurface and defining a cavity with a cavity bottom, where the cavitybottom includes a central portion; (2) an upper sloped portion disposedadjacent to the upper surface of the peripheral edge region and facingaway from the cavity; and (3) a lower sloped portion disposed adjacentto the upper sloped portion and facing away from the cavity. Theplurality of leads is disposed around the die pad, and each of theplurality of leads includes: (1) an upper surface; (2) a lower surface;(3) an upper sloped portion disposed adjacent to the upper surface ofthe each of the plurality of leads; and (4) a lower sloped portiondisposed adjacent to the lower surface of the each of the plurality ofleads. The semiconductor chip is disposed on the central portion of thecavity bottom and is electrically coupled to the plurality of leads. Thepackage body is formed over the semiconductor chip and the plurality ofleads so that the package body substantially fills the cavity andsubstantially covers the upper sloped portions of the die pad and theplurality of leads. The package body is also formed over thesemiconductor chip and the plurality of leads so that the lower slopedportions of the die pad and the plurality of leads at least partiallyextend outwardly from a lower surface of the package body.

In another innovative aspect, the invention relates to a method ofmaking a semiconductor package. In one embodiment, the method includesproviding a metal carrier plate including (1) a base including an uppersurface and a lower surface; (2) a central protrusion having an uppersurface, extending upwardly from the base, and defining a central regionof the upper surface of the base, the central region having a centralportion; (3) a plurality of peripheral protrusions, each having an uppersurface, extending upwardly from the base, and being disposed around thecentral protrusion; (4) a first metal coating formed on the uppersurfaces of the central protrusion and the plurality of peripheralprotrusions; and (5) a second metal coating formed on the lower surfaceof the metal carrier plate below the central region, the centralprotrusion, and the plurality of peripheral protrusions. The methodfurther includes attaching a semiconductor chip to the central portion,electrically coupling the semiconductor chip to at least a firstprotrusion included in the plurality of peripheral protrusions, andforming a package body over the semiconductor chip and the plurality ofperipheral protrusions. The method further includes etching areas on thelower surface of the metal carrier plate without the second metalcoating formed thereon such that: (1) the plurality of peripheralprotrusions and the central protrusion are separated from one another soas to form a plurality of leads and a die pads where the die padincludes the central protrusion and the central region; (2) each of theplurality of leads includes a lower sloped portion disposed adjacent toa lower surface of the each of the plurality of leads; (3) the die padincludes a lower sloped portion disposed adjacent to a lower surface ofthe die pad; and (4) the lower sloped portions of the die pad and theplurality of leads at least partially extend outwardly from a lowersurface of the package body.

In a further innovative aspect, the invention relates to a semiconductorpackage. In one embodiment, the semiconductor package includes a diepad, a plurality of leads, a semiconductor chip, and a package body. Thedie pad includes: (1) a base including an upper surface and a lowersurface; (2) a protrusion extending upwardly from the base and disposedadjacent to a peripheral edge of the base, where the protrusion includesan upper surface; and (3) a first side surface extending between theupper surface of the protrusion and the lower surface of the base, wherethe first side surface includes a first peak that is disposed closer tothe lower surface of the base than to the upper surface of theprotrusion. The plurality of leads is disposed around the die pad, andat least one of the plurality of leads includes a second side surfaceincluding a second peak. The semiconductor chip is disposed on the uppersurface of the base and is electrically coupled to the plurality ofleads. The package body is formed over the semiconductor chip and theplurality of leads so that the package body substantially covers theupper surface of the base, at least a portion of the first side surfaceabove the first peak, and at least a portion of the second side surfaceabove the second peak. The package body is also formed over thesemiconductor chip and the plurality of leads so that at least a portionof the first side surface below the first peak and at least a portion ofthe second side surface below the second peak protrude from a lowersurface of the package body.

Other aspects and embodiments of the invention are also contemplated.The foregoing summary and the following detailed description are notmeant to restrict the invention to any particular embodiment but aremerely meant to describe some embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the nature and objects of some embodimentsof the invention, reference should be made to the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 illustrates a cross-sectional view of a semiconductor package, inaccordance with one embodiment of the present invention;

FIG. 2 illustrates a cross-sectional, enlarged view of a die pad, inaccordance with one embodiment of the present invention;

FIG. 3 illustrates a cross-sectional, enlarged view of a lead, inaccordance with one embodiment of the present invention;

FIG. 4 illustrates a top view of a portion of a metal carrier plate, inaccordance with one embodiment of the present invention;

FIG. 5 illustrates processing operations for making a metal carrierplate, in accordance with one embodiment of the present invention;

FIG. 6 illustrates processing operations for making a semiconductorpackage, in accordance with one embodiment of the present invention;

FIG. 7 illustrates processing operations for making a semiconductorpackage including multiple stacked dies or chips, in accordance with oneembodiment of the present invention;

FIG. 8 illustrates processing operations for making a semiconductorpackage and surface mounting the semiconductor package, in accordancewith one embodiment of the present invention;

FIG. 9 illustrates processing operations for making a semiconductorpackage and surface mounting the semiconductor package, in accordancewith another embodiment of the present invention; and

FIG. 10 illustrates a top view of a portion of a metal carrier plateincluding a power segment separated from a ground ring, in accordancewith one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a cross-sectional view of a semiconductor package100, in accordance with one embodiment of the present invention. Thepackage 100 includes a die pad 101 with a peripheral edge region 114that defines a cavity 111 with a cavity bottom 112. The peripheral edgeregion 114 may completely surround the cavity 111, but also canpartially surround the cavity 111 for certain implementations. Thecavity bottom 112 includes a central portion 112 a. The cavity bottom112 may also include a recess 112 b around the central portion 112 a.The central portion 112 a may be approximately centrally located withinthe cavity bottom 112, but need not be if, for example, the recess 112 bis of non-uniform width. The recess 112 b may completely surround thecentral portion 112 a, but also can partially surround the centralportion 112 a for certain implementations. A chip 102 is attached to thecavity bottom 112 by an adhesive layer (not shown). The adhesive layermay be a conductive or a non-conductive adhesive material, such asnon-conductive epoxy. In the illustrated embodiment, the chip 102 isattached to the central portion 112 a. Bonding pads 106 on the activesurface of the chip 102 are electrically coupled to leads 171 throughbonding wires 104, and may also be electrically coupled to at least partof the peripheral edge region 114 through bonding wires 104. The leads171 are disposed around the die pad 102, and may completely or partiallysurround the die pad 101.

FIG. 2 illustrates a cross-sectional, enlarged view of the die pad 101,in accordance with one embodiment of the present invention. The die pad101 includes a side surface 208, which may completely or partiallyextend around a circumference of the die pad 101. In the illustratedembodiment, the side surface 208 includes an upper sloped portion 208 cdisposed adjacent to an upper surface 151 of the peripheral edge region114 and facing away from the cavity 111. The side surface 208 alsoincludes a lower sloped portion 208 a disposed adjacent to the uppersloped portion 208 c and facing away from the cavity 111. The peripheraledge region 114 also includes an upper sloped portion 218 disposedadjacent to the upper surface 151 and facing toward the cavity 111.Sloped portions 208 a, 208 c, and 218 may be linear or curved, and aretypically non-perpendicular to the upper surface 151 of the peripheraledge region 114. The side surface 208 also includes a peak 208 b.

FIG. 3 illustrates a cross-sectional, enlarged view of a lead 171, inaccordance with one embodiment of the present invention. The lead 171includes a side surface 308, which may completely or partially extendaround a circumference of the lead 171. In the illustrated embodiment,the side surface 308 includes an upper sloped portion 308 e disposedadjacent to an upper surface 155 of the lead 171. The side surface 308also includes a lower sloped portion 308 a disposed adjacent to a lowersurface 157 of the lead 171. Sloped portions 308 a and 308 c may belinear or curved, and are typically non-perpendicular to the uppersurface 155 and the lower surface 157 of the lead 171. The side surface308 also includes a peak 308 b.

Referring back to FIG. 1 along with FIG. 2 and FIG. 3, a package body108 is formed over the chip 102, the die pad 101, and the leads 171 sothat the package body 108 substantially fills the cavity 111 andsubstantially covers the upper sloped portions 218 of the peripheraledge region 114. The package body 108 also substantially covers theupper sloped portions 208 c of the die pad 101, and the upper slopedportions 308 c of the leads 171. In this context, the term“substantially” indicates, in part, that the cavity 111 having the chip102 disposed on the cavity bottom 112 is filled by the package body 108;the term also indicates that the package body 108 typically fills thecavity 111 to sufficiently minimize or reduce pockets of air andmoisture, and covers the chip 102, the bonding wires 104, and the uppersloped portions 208 c, 218, and 308 c to provide sufficient protectionfrom oxidation, moisture, and other environmental conditions to meetpackaging application requirements. In the illustrated embodiment, thelower sloped portions 208 a of the die pad 101 and the lower slopedportions 308 a of the leads 171 at least partially extend outwardly froma lower surface 160 of the package body 108. Alternatively, either thelower sloped portions 208 a of the die pad 101 or the lower slopedportions 308 a of the leads 171 may at least partially extend outwardlyfrom the lower surface 160 of the package body 108.

The sloping of the upper sloped portions 208 c, 218, and 308 c cansignificantly increase the area of contact, and thus the adhesionbetween the package body 108 and the die pad 101, and between thepackage body 108 and the leads 171. This can thereby enhance the moldlocking of the die pad 101 and the leads 171 in the package body 108.This can also prolong the path and time for moisture diffusion into thepackage 100.

In the illustrated embodiment, the upper sloped portions 208 c and 308 chave substantially concave profiles. In this context, the term“substantially” is used to indicate that the upper sloped portions 208 cand 308 c are generally concave, i.e. rounded inwards toward the centerof the die pad 101 and the leads 171, but that the upper sloped portions208 c and 308 c may include surface non-uniformities or roughness in theform of small peaks, such as asperities, that may be rounded outwardsfrom the center of the die pad 101 and the leads 171. For example, FIG.3 shows that the upper sloped portion 308 c of the lead 171 has anoverall shape that is generally rounded inward toward the center of thelead 171. At the same time, the upper sloped portion 308 c is roughlytextured with numerous asperities. These asperities engage the packagebody 108 during molding and thereby enhance mold locking of the lead 171in the package body 108. These asperities can be formed throughprecisely controlled etching or some other suitable process. Similarly,the lower sloped portions 208 a and 308 a may have substantially concaveprofiles. In this context, the term “substantially” is used to indicatethat the lower sloped portions 208 a and 308 a are generally concave,i.e. rounded inwards toward the center of the die pad 101 and the leads171. For example, FIG. 2 shows that the lower sloped portion 308 c ofthe lead 171 has an overall shape that is generally rounded inwardtoward the center of the lead 171. Similarly, the upper sloped portions218 may have substantially concave profiles. In this context, the term“substantially” is used to indicate that the upper sloped portions 218are generally concave, i.e. rounded inwards toward the center of theperipheral edge region 114. For example, FIG. 2 shows that the uppersloped portion 218 of the peripheral edge region 114 has an overallshape that is generally rounded inward toward the center of theperipheral edge region 114.

It will be understood that the die pad 101 may be alternativelydescribed. For example, in FIG. 2, the die pad 101 includes a base 202with an upper surface 212 and a lower surface 153. A protrusion 213 withan upper surface 151 extends upwardly from the base 202 and is disposedadjacent to a peripheral edge of the base 202. A side surface 208extends between the tipper surface 151 of the protrusion 213 and thelower surface 153 of the base 202, and includes a peak 208 b. A sidesurface 218 extends between the upper surface 151 of the protrusion 213and the upper surface 212 of the base 202. In the illustratedembodiment, the upper surface 212 of the base 202 includes a centralregion 212 a on which the chip 102 is disposed. The upper surface 212may also include a recess 212 b around the central region 212 a. Thecentral region 212 a may be approximately centrally located within theupper surface 212, but need not be it for example, the recess 212 b isof non-uniform width. The recess 212 b may completely surround thecentral region 212 a, but also can partially surround the central region212 a for certain implementations.

It will also be understood that the package body 108 may bealternatively described. For example, in FIG. 1, FIG. 2, and FIG. 3, thepackage body 108 is formed over the chip 102, the die pad 101, and theleads 171 so that the package body 108 substantially covers the uppersurface 212 of the base 202 and the side surface 218. The package body108 also substantially covers at least a portion of the side surface 208above the peak 208 b, and at least a portion of the side surface 308above the peak 308 b. In this context, the term “substantially”indicates, in part, that the upper surface 212 of the base 202 havingthe chip 102 disposed thereon is covered by the package body 108; theterm also indicates that the package body 108 typically covers the chip102, the bonding wires 104, the upper surface 212 of the base 202, theside surface 218 the portion of the side surface 208 above the peak 208b, and the portion of the side surface 308 above the peak 308 b toprovide sufficient protection from oxidation, moisture, and otherenvironmental conditions to meet packaging application requirements. Atleast a portion of the side surface 208 below the peak 208 b protrudesfrom the lower surface 160 of the package body 108. Similarly, at leasta portion of the side surface 308 below the peak 308 b protrudes fromthe lower surface 160 of the package body 108.

The package 100 may further include a metal coating 116 disposed on theupper surface 151 of the peripheral edge region 114 as shown in FIG. 1,alternatively described as disposed on the upper surface 151 of theprotrusion 213 as shown in FIG. 2. The package 100 may also include ametal coating 117 disposed on the lower surface 153 of the die pad 101as shown in FIG. 1, alternatively described as disposed on the lowersurface 153 of the base 202 as shown in FIG. 2. The package 100 may alsoinclude a metal coating 126 disposed on the upper surfaces 155 of theleads 171 as shown in FIG. 1, and a metal coating 127 disposed on thelower surfaces 157 of the leads 171 as shown in FIG. 1. These metalcoatings can be disposed using techniques such as electrolytic platingand electroless plating. It is desirable that these metal coatingsadhere well to the surfaces of the die pad 101 and the leads 171, enableeffective wire bonding with bonding wires 104, and protect the lowersurfaces of the die pad 101 and the leads 171 from oxidation and otherenvironmental conditions. With these goals in mind, the metal coatingscan include a layer of nickel in contact with the surfaces 151 and 153of the die pad 101 and the surfaces 155 and 157 of the leads 171, and alayer of gold or palladium covering the layer of nickel. Alternatively,the metal coatings may include a layer of an alloy of nickel and eitherone of, or both, gold and palladium.

Referring to FIG. 1 along with FIG. 2 and FIG. 3, a standoff distance148 can refer to the distance that the lower sloped portions 208 a ofthe die pad 101 and/or the lower sloped portions 308 a of the leads 171extend outwardly from the lower surface 160 of the package body 108,and, for certain implementations, can include or otherwise account for athickness of the metal coatings 117 and 127. Alternatively, the standoffdistance 148 can refer to the distance that the portion of the sidesurface 208 below the peak 208 b and/or the portion of the side surface308 below the peak 308 b protrude from the lower surface 160 of thepackage body 108. The protrusion of the die pad 101 and/or the leads 171from the lower surface 160 of the package body 108 can enhance thesolderability of the die pad 101 and the leads 171 to a PCB by exposingadditional area on the die pad 101 and/or the leads 171 to which soldercan attach. This can increase the reliability of surface mounting of thepackage 100 to the PCB. In one embodiment, the peak 208 b is disposedcloser to the lower surface 153 of the base 202 than to the uppersurface 151 of the protrusion 213, and the peaks 308 b are disposedcloser to the lower surfaces 157 of the leads 171 than to the uppersurfaces 155 of the leads 171.

For certain implementations, the standoff distance 148 is between abouttwenty and about fifty percent or between about twenty-five and aboutforty-five percent of a thickness 142 of the die pad 101 and/or at leastone of the leads 171, although the standoff distance 148 is notconstrained to this range and, for other implementations, may be betweenabout five percent and about seventy-five percent of the thickness 142.The thickness 142 of the die pad 101 can be measured as the distancebetween the upper surface 151 of the peripheral edge region 114 and thelower surface 153 of the die pad 101. If metal coatings 116 and 117 aredisposed on surfaces 151 and 153 of the die pad 101, as is typically thecase, then the thickness 142 can be measured as the distance between theupper surface 150 of the metal coating 116 and the lower surface 152 ofthe metal coating 117. Similarly, for a lead 171, if metal coatings 126and 127 are disposed on surfaces 155 and 157 of the lead 171, as istypically the case, then the thickness 142 can be measured as thedistance between the upper surface 154 of the metal coating 126 and thelower surface 156 of the metal coating 127. As described herein, variousdistances can be measured relative to the surfaces of metal coatings116, 117, 126, and 127. However, it will be understood that thesedistances can be similarly measured relative to the surfaces 151 and 153of the die pad 101 or the surfaces 155 and 157 of the leads 171, if anyor all of the metal coatings 116, 117, 126, and 127 are not present.

In one embodiment, the thickness 142 of the die pad 101 including metalcoatings 116 and 117 is substantially equal to that of at least one lead171 including metal coatings 126 and 127, and is about 0.125millimeters. In this case, the standoff distance 148 by which the diepad 101 and the at least one lead 171 protrudes from the lower surface160 of the package body 108 is between about 0.025 millimeters and about0.0625 millimeters or between about 0.03 millimeters and about 0.05millimeters. Also, the peak 208 b of the side surface 208 of the die pad101 is substantially level with the peak 308 b of the side surface 308of the at least one lead 171. In an alternative embodiment, thethickness 142 of the die pad 101 and/or the at least one lead 171 may beabove or below 0.125 millimeters.

As the standoff distance 148 becomes a larger percentage of thethickness 142 within the range of about twenty to about fifty percent,the reliability of mold locking of the die pad 101 and/or the leads 171in the package body 108 typically tends to decrease, while thereliability of surface mounting of the package 100 on a PCB typicallytends to increase. At the same time, the duration and cost of bottomside etching (see FIG. 6) typically increases. The choice of thestandoff distance 148 as a percentage of the thickness 142 can be atradeoff between these factors.

A mold cap 140 can refer to the distance between an upper surface 164 ofthe package body 108 and the upper surface 150 of the metal coating 116.Similarly, for a lead 171, the mold cap 140 can be measured as thedistance between the upper surface 164 of the package body 108 and theupper surface 154 of the metal coating 126. The mold cap 140 istypically large enough so that the chip 102 and the bonding wires 104are enclosed within the package body 108. In one embodiment, the moldcap 140 is between about 0.4 millimeters and about 1 millimeter, such asabout 0.675 millimeters, although the mold cap 140 can be smaller solong as the chip 102 and the bonding wires 104 remain sufficientlyenclosed within the package body 108. The inclusion of the cavity 111 inthe die pad 101 can enable the chip 102 to be disposed on the centralportion 112 a of the cavity bottom 112 as shown in FIG. 1.Alternatively, the chip 102 can be disposed on the central region 212 aof the upper surface 212 of the base 202 as shown in FIG. 2.

In FIG. 1 and FIG. 2, distance 206 measures a depth of the centralportion 112 a (or central region 212 a) relative to the upper surface150 of the metal coating 116. Distance 204 measures a depth of therecess 112 b (or recess 212 b) relative to the upper surface 150 of themetal coating 116. For certain implementations, the distance 206 isbetween about fifty-five and about eighty percent of the distance 204,although the distance 206 is not constrained to this range. In oneembodiment, the distance 206 is about 0.065 millimeters and the distance204 is about 0.095 millimeters Both the distances 204 and 206 may varyabove or below these values, so long as the distances 204 and 206 remainless than the thickness 142 of the die pad 101 by some margin, such asabout 0.01 millimeters. Preferably, the central portion 112 a (orcentral region 212 a) and the recess 112 b (or recess 212 b) are theresult of etching (see FIG. 5), rather than plating to build up theperipheral edge region 114 (or central protrusion 213). Plating may beboth more costly and time consuming than the etching processsubsequently described and shown in FIG. 5.

By disposing the chip 102 on the cavity bottom 112 (or upper surface 212of the base 202), the top surface of the chip 102 is lower by thedistance 206 relative to the upper surface 150 of the metal coating 116,and relative to the upper surfaces 154 of the metal coating 126 on eachlead 171. As a result, the mold cap 140 can be reduced, which can makethe package 100 thinner. In addition, the lower surface of the chip 102is closer by distance 206 to the lower surface 152 of the metal coating117. This can enhance heat dissipation from the chip 102 through the diepad 101.

Referring to FIG. 1 along with FIG. 2 and FIG. 3, a height difference146 refers to the distance between a plane 166 through the highest pointof the central portion 112 a (or central region 212 a) and the lowersurface 160 of the package body 108. The lower surface 160 of thepackage body 108 typically corresponds, at least approximately, to thelower surface of the package body 108 within the recess 112 b (or recess212 b). For certain implementations, the height difference 146 isbetween about 0.02 millimeters and about 0.04 millimeters, although theheight difference 146 is not constrained to this range. For certainimplementations, the upper surface 150 of the metal coating 116 can bedisposed between about 0.05 millimeters and about 0.08 millimeters abovethe plane 166, but is not constrained to this range. Also, the peak 208b of the side surface 208 of the die pad 101 and the peak 308 b of theside surface 308 of at least one lead 171 may be disposed below theplane 166. The height difference 146 and the positioning of the peaks208 b and 308 b relative to the plane 166 can be controlled by etching,such as through a top side etching process (see FIG. 5).

Distance 144 refers to the minimum distance from side surface 162 of thepackage body 108 to side surfaces 308 of any of the leads 171. In theembodiment of FIG. 1, distance 144 is illustrated as the distance fromthe side surface 162 to the peak 308 b of the leftmost outer lead 171A.For certain implementations, the distance 144 is between about 0.1millimeters and about 0.3 millimeters, although the distance 144 is notconstrained to this range. The portion of the package body 108 to theleft of leftmost outer lead 171A (and similarly to the right ofrightmost outer lead 171B) can prevent peeling and detachment of theouter leads 171A and 171B during singulation (see FIG. 6) and during useof the package 100.

Lead spacing 145, also referred to as terminal pitch, refers to thedistance between the centers of a pair of adjacent leads 171. Forcertain implementations, the lead spacing 145 is between about 0.35 andabout 0.55 millimeters, although the lead spacing 145 is not constrainedto this range. The lead spacing 145 can be controlled by etching, suchas through a top side etching process (see FIG. 5).

In FIG. 3, a protective layer 310 is shown substantially covering thelower sloped portion 308 a of at least one of the plurality of leads171. In this context, the term “substantially” indicates that theprotective layer 310 typically covers the lower sloped portion 308 a ofthe at least one lead 171 to sufficiently protect the underlying metalfrom oxidation, moisture, and other environmental conditions to meetpackaging application requirements. The package body substantiallycovers the upper sloped portion 308 c (or the portion of the sidesurface 308 above the peak 308 b), but does not entirely cover the lowersloped portion 308 a (or the portion of the side surface 308 below thepeak 308 b), or at least does not cover that part of the lower slopedportion 308 a that extends outwardly from the lower surface 160 of thepackage body 108. As a result, the protective layer 310 is included inaddition to the protective metal coating 127 (see FIG. 1) on the lowersurface 157 of the lead 171 to prevent or reduce oxidation and corrosionof the underlying metal, which is typically copper or a copper alloy. Asimilar protective layer may be applied to the lower sloped portion 208a of the die pad 101 (or the portion of the side surface 208 below thepeak 208 b). In FIG. 2, a protective layer 210 is shown substantiallycovering the lower sloped portion 208 a of the die pad 101. Theprotective layer 210, along with the protective metal coating 117 (seeFIG. 1) on the lower surface 153 of the die pad 101, sufficientlyprotects the underlying metal of the die pad 101 to meet packagingapplication requirements.

In one embodiment, the protective layers 210 and 310 can include a metalcoating. The metal coating may include at least one of a layer of tin, alayer of nickel, and a layer of gold. Alternatively, the metal coatingmay include a layer of an alloy of two or more of these metals. Themetal coating may be attached to the lower sloped portions 208 a and 308a using immersion, electrolytic plating, electroless plating, or anyother suitable process.

In another embodiment, the protective layers 210 and 310 can include asolder material. The solder material may include a solder paste. Thesolder paste may be selectively disposed on the lower sloped portions208 a and 308 a, while the protective metal coatings 117 and 127(without the solder paste) substantially cover the lower surface 153 ofthe die pad 101 and the lower surface 157 of at least one lead 171. Inthis context, the term “substantially” indicates that the protectivemetal coatings 117 and 127 typically cover the lower surfaces 153 and157 to sufficiently protect the underlying metal from oxidation,moisture, and other environmental conditions to meet packagingapplication requirements. The protective metal coatings 117 and 127 mayalso protect the underlying metal during etching, as described andillustrated in FIG. 5. Alternatively, the solder paste may be disposedon both the lower sloped portions 208 a and 308 a and the lower surfaces153 and 157. The solder paste is then dried or hardened. Alternatively,the solder paste may be ref owed and hardened into a solder bump.

In another embodiment, the protective layers 210 and 310 can include anorganic solderability preservative (OSP) layer. The OSP layer may beattached to the lower sloped portions 208 a and 308 a using immersion orrinsing with a solution based on an organic material, or any othersuitable process. The organic material may be an imidazole basedmaterial. The OSP layer may be selectively disposed on the lower slopedportions 208 a and 308 a, or alternatively may be disposed on the lowersloped portions 208 a and 308 a, the lower surface 153 of the die pad101, and the lower surface 157 of at least one lead 171. If the OSPlayer is disposed on the lower surfaces 153 and 157, an additionalprocessing operation to remove the OSP layer may be omitted, as the OSPlayer typically evaporates at temperatures encountered when solderingthe die pad 101 and at least one lead 171 to a PCB.

The use of a solder material and/or an organic material as part ofprotective layers 210 and 310 is desirable for at least two reasons.First, typical solder materials and organic materials are less costlythan metals such as nickel, gold, and tin. Second, solder materials andorganic materials can be applied to the die pad 101 and at least onelead 171 without using electrolytic or electroless plating processes,which can simplify the creation of the protective layers 210 and 310.

FIG. 4 illustrates a top view of a portion of a metal carrier plate 400,in accordance with one embodiment of the present invention. The metalcarrier plate 400 may be formed as described in FIG. 5. The metalcarrier plate 400 includes a base 402, and the base 402 has a centralprotrusion 404 extending upwardly from the base 402. In this context,the term “central” indicates that the protrusion 404 may beapproximately centrally located within the portion of the metal carrierplate 400 shown in FIG. 4. However, the portion of the metal carrierplate 400 shown in FIG. 4 can be variously located within the metalcarrier plate 400, including bordering the edge of the metal carrierplate 400. Although the central protrusion 404 is shown as extendingcompletely around a circumference of the base 402 in FIG. 4, the centralprotrusion 404 may extend partially around the base 402 in anotherembodiment. A plurality of peripheral protrusions 406 are disposedaround the base 402. Although the peripheral protrusions 406 are shownas substantially completely surrounding the base 402 in FIG. 4, theperipheral protrusions 406 may partially surround the base 402 inanother embodiment. A corner peripheral protrusion 408 at one of thecorners of the portion of the metal carrier plate 400 may be of adifferent shape and/or size from the other peripheral protrusions 406.This corner peripheral protrusion 408 may serve as a recognition mark tofacilitate the orientation, during surface mounting, of a resultingpackage.

The hatched portions of the metal carrier plate 400 (404, 406, and 408)have not been etched, and therefore protrude from the other portions ofthe metal carrier plate 400 (including part of 402), which have beenetched from the top side (see FIG. 5). In one embodiment, the peripheralprotrusions 406 are disposed in at least three rows on at least one sideof the base 402. After bottom side etching (see FIG. 6), the base 402and the peripheral protrusions 406 are separated and formed into the diepad 101 and the leads 171, as previously described in FIGS. 1 through 3.Since the peripheral protrusions 406 need not be connected to adisposable portion of a leadframe, as is typically the case for a QFNleadframe, the creation of multiple rows of leads 171 using theprocessing operations of FIGS. 5 and 6 is significantly more scalable totwo or more such rows than is typical QFN processing.

In one embodiment, after bottom side etching (see FIG. 6), the centralprotrusion 404 may include a ground segment to which a chip (e.g., thechip 102) is electrically coupled using bonding wires (e.g., the bondingwires 104). The ground segment may be a ground ring that includes theentire central protrusion 404. In another embodiment, the ground segmentmay be a first portion 404 a of the central protrusion 404, and a powersegment may be a second portion 404 b of the central protrusion 404. Inthis case, a first portion of the base 402 connected to the groundsegment 404 a can be electrically isolated from a second portion of thebase 402 connected to the power segment 404 b. The electrical isolationmay be performed using etching, singulation, or any other suitableprocess to physically separate the first portion of the base 402 fromthe second portion of the base 402, such as along the dotted line 410.

It will be understood that the portion of the metal carrier plate 400shown in FIG. 4 may be alternatively described. For example, the metalcarrier plate 400 may include a die receiving area 402 with a peripheraledge region 404. A plurality of peripheral bulges 406 may be disposedaround the die receiving area 402.

FIG. 5 illustrates processing operations for making a metal carrierplate 500, in accordance with one embodiment of the present invention. Afirst photoresist layer 506 is formed on an upper surface 502 of acopper plate 501, and a second photoresist layer 508 is formed on alower surface 504 of the copper plate 501. The photoresist layers 506and 508 are formed by coating, printing, or any other suitabletechnique. Predetermined or selected portions of the photoresist layers506 and 508 are photoimaged and developed so as to create first exposedportions 510 and second exposed portions 512 of the copper plate 501.The photoresist layers 506 and 508 may be photochemically defined usinga photomask (not shown).

A first metal coating 514 is then formed on the exposed portions 510,and a second metal coating 516 is formed on the exposed portions 512.The metal coatings 514 and 516 can have the same characteristics aspreviously described for metal coatings 116, 117, 126, and 127. Thephotoresist layers 506 and 508 are then stripped. Areas 518 of the uppersurface 502 of the copper plate 501 without the protection of the metalcoating 514 are then etched to form the metal carrier plate 500,including the previously described central region 212 a, centralprotrusion 213, and peripheral protrusions 406. Alternatively, theetching may form the previously described die receiving area 402 andperipheral bulges 406 as part of the metal carrier plate 500. Thisetching operation may be referred to as top side etching.

The metal carrier plate 500 typically includes multiple interconnectedportions, such as portions 500 a and 500 b. Each portion may include thepreviously described central region 212 a, central protrusion 213, andperipheral protrusions 406.

FIG. 6 illustrates processing operations for making the semiconductorpackage 100, in accordance with one embodiment of the present invention.A chip 102 is attached to a central region 212 a (or die receiving area402) of each portion of a metal carrier plate 500, such as portions 500a and 500 b. Each chip 102 is attached using an adhesive layer (notshown), as previously described. Each chip 102 is then electricallycoupled to peripheral protrusions 406 (or peripheral bulges 406) throughbonding wires 104. A package body 108 is then formed over each chip 102and each of the peripheral protrusions 406. The package body 108 may becomposed of a synthetic resin, and may be formed through molding methodssuch as transfer molding. Areas 620 of the lower surface of the metalcarrier plate 500 without the protection of the metal coating 516 arethen etched to separate the peripheral protrusions 406 and the centralprotrusion 213 to form the previously described leads 171 and die pad101. This etching operation may be referred to as bottom side etching.The leads 171 and the die pad 101 may be formed in each of multipleconnected packages sharing package body 108, such as connected packages600 a and 600 b. Through singulation, the connected packages 600 a and600 b may be separated into packages 100 a and 100 b. Singulation can becarried out by, for example, sawing, which can create substantiallyvertical side surfaces of the packages 100 a and 100 b as shown in FIG.6.

FIG. 7 illustrates processing operations for making a semiconductorpackage 100 including multiple stacked dies or chips, in accordance withone embodiment of the present invention. A first chip 102 a is attachedto a central region 212 a (or die receiving area 402) of each portion ofa metal carrier plate 500, such as portions 500 a and 500 b. Each firstchip 102 a is attached using an adhesive layer (not shown), aspreviously described. Each first chip 102 a may then be electricallycoupled to at least one portion of a central protrusion 213 (orperipheral edge region 404) through bonding wires 104 a. In anotherembodiment, each first chip 102 a may be electrically coupled to one ormore peripheral protrusions 406.

An attachment layer 700 is then disposed on the upper surface of eachfirst chip 102 a. A second chip 102 b is then coupled to the uppersurface of each first chip 102 a by the attachment layer 700. Eachsecond chip 102 b may then be electrically coupled to peripheralprotrusions 406 through bonding wires 104 b. In another embodiment, eachsecond chip 102 b may be electrically coupled to at least one portion ofthe central protrusion 213. Any peripheral protrusion 406 or portion ofthe central protrusion 213 to which a second chip 102 b is coupled canbe electrically isolated from any peripheral protrusion 406 or portionof the central protrusion 213 to which a corresponding first chip 102 ais coupled.

The package body 108 is then formed over each set of stacked chips 102 aand 102 b and each of the peripheral protrusions 406. Areas 620 of thelower surface of the metal carrier plate 500 without the protection ofthe metal coating 516 are then etched to separate the peripheralprotrusions 406 and the central protrusion 213 to form the previouslydescribed leads 171 and die pad 101. The leads 171 and the die pad 101may be formed in each of multiple connected packages sharing packagebody 108, such as connected packages 600 a and 600 b. Throughsingulation, the connected packages 600 a and 600 b may be separatedinto packages 100 a and 100 b.

In one embodiment, the attachment layer 700 includes an adhesive layer.The adhesive layer may be a conductive or a non-conductive adhesivematerial, such as a non-conductive epoxy. The adhesive layer may be aliquid-type adhesive layer or a film-type adhesive layer, such as adouble-sided tape. The adhesive layer may also be a film-on-wireadhesive layer, which has similar characteristics but is typicallythicker than the film-type adhesive layer.

In one embodiment, chip 102 b extends beyond the peripheral edge of chip102 a. One advantage of the film-on-wire adhesive layer is that thisadhesive layer can be sufficiently thick so that when chip 102 b isattached to this adhesive layer, there is still sufficient clearance forbonding wires 104 a attached to chip 102 a. If the film-on-wire adhesivelayer is not used, then the attachment layer 700 may include a spacer inaddition to the liquid-type and/or film-type adhesive layer. The purposeof the spacer is to space apart chips 102 a and 102 b so that there issufficient clearance for bonding wires 104 a attached to chip 102 a.

As described previously, a resulting package 100 can be made thinner bydisposing the chip 102 on the cavity bottom 112 (or upper surface 212 ofthe base 202). For a package 100 with stacked chips such as in FIG. 7,it may be especially important to take advantage of the additional spaceprovided by the cavity 111 to make the package 100 thinner. In addition,the ordering of stacking may be important. For example, in FIG. 7, thechip 102 b extends beyond the cavity 111 and partly covers over theperipheral edge region 114 of the die pad 101, so the chip 102 b couldnot be disposed on the cavity bottom 112. However, the chip 102 a issized so that it can be disposed on the cavity bottom 112. In this case,the chip 102 b may be stacked on top of the chip 102 a if the height ofthe chip 102 a plus the height of the attachment layer 700 is largeenough to provide sufficient clearance above the upper surface 150 ofthe metal coating 116 disposed on the peripheral edge region 114, andabove the bonding wires 104 a.

FIG. 8 illustrates processing operations for making a semiconductorpackage 100 and surface mounting the semiconductor package 100, inaccordance with one embodiment of the present invention. As describedpreviously, leads 171 and die pad 101 may be formed in each of multipleconnected packages sharing a package body 108, such as connectedpackages 600 a and 600 b. In this embodiment, a solder paste 802 isdisposed to substantially cover a sloped etched area 308 a of at leastone lead 171, and a lower surface 156 of a metal coating 127 disposed onthe lower surface 157 of that lead 171. The solder paste 802 is thensolidified for defining a solder interface 802 for subsequent surfacemounting. Solder paste 800 may also be disposed to substantially cover asloped etched area 208 a of the die pad 101, and a lower surface 152 ofa metal coating 117 of the die pad 101. Through singulation, theconnected packages 600 a and 600 b are then separated into packages 100a and 100 b.

For surface mounting the package 100 a, the solder interfaces 800 and802 may be reflowed to form liquefied solder masses 804 and 806. Theliquefied solder masses 804 and 806 are then placed into contact with aPCB 808 and hardened. The solder interfaces 800 and 802 typicallycontain enough solder so that, upon reflow soldering and surfacemounting of the package 100 a, the solder acts as a protective layer forthe sloped etched areas 208 a and 308 a by substantially covering, theseareas.

In addition to the use of the solder as a protective layer, anotheradvantage of the surface mounting process of FIG. 8 is that surfacemounting of the package 100 a can be achieved by reflowing the solderinterfaces 800 and 802. This removes the need for additional solderpaste on the PCB 808 as part of surface mounting of the package 100 a.

FIG. 9 illustrates processing operations for making a semiconductorpackage 100 and surface mounting the semiconductor package 100, inaccordance with another embodiment of the present invention. In thisembodiment, the package 100 is provided without solder interfaces 800and 802 for surface mounting. A sloped etched area 208 a of a die pad101 and a sloped etched area 308 a of at least one lead 171 may besubstantially covered with a protective layer such as an OSP layer, asdescribed previously. Subsequently, solder paste 900 is applied on a PCB908 in preparation for surface mounting of the package 100. Aftersurface mounting of the package 100, the solder paste is reflowed andthen hardened into solder masses 902 attaching the package 100 to thePCB 908.

As described previously, enough solder paste 900 can be applied on thePCB 908 so that upon surface mounting of the package 100 and reflowsoldering, the solder acts as a protective layer for the sloped etchedareas 208 a and 308 a by substantially covering those areas.

FIG. 10 illustrates a top view of a portion of a metal carrier plate1000 including a power segment 1002 separated from a ground ring 1004,in accordance with one embodiment of the present invention.

While the methods disclosed herein have been described with reference toparticular operations performed in a particular order, it will beunderstood that these operations may be combined, sub-divided, orre-ordered to form an equivalent method without departing from theteachings of the invention. Accordingly, unless specifically indicatedherein, the order and grouping of the operations are not limitations ofthe invention.

The foregoing description, for purposes of explanation, used specificnomenclature to provide a thorough understanding of the invention.However, it will be apparent to one skilled in the art that specificdetails are not required in order to practice the invention. Thus, theforegoing descriptions of specific embodiments of the invention arepresented for purposes of illustration and description. They are notintended to be exhaustive or to limit the invention to the precise formsdisclosed; many modifications and variations are possible in view of theabove teachings. The embodiments were chosen and described in order tobest explain the principles of the invention and its practicalapplications, they thereby enable others skilled in the art to bestutilize the invention and various embodiments with various modificationsas are suited to the particular use contemplated. It is intended thatthe following claims and their equivalents define the scope of theinvention.

What is claimed is:
 1. A semiconductor package comprising: a die padincluding: a die mounting region; a peripheral region circumscribing acavity with a cavity bottom, the peripheral region including a slopedexterior facing surface and a sloped interior facing surface, wherein:the cavity bottom includes the die mounting region and a recesscontiguously circumscribing the die mounting region; the recess isformed at a junction of the sloped interior facing surface and the diemounting region such that the sloped interior facing surface and asurface of the recess correspond to a continuous, curved surface; andthe sloped exterior facing surface includes an upper sloped surface, alower sloped surface, and an apex at a junction of the upper slopedsurface and the lower sloped surface; a plurality of leads disposedaround the die pad, wherein each of the plurality of leads includes anupper sloped portion and a lower sloped portion; and a firstsemiconductor chip disposed on the die mounting region and electricallycoupled to the plurality of leads; and a package body formed over thefirst semiconductor chip and the plurality of leads so that the packagebody substantially fills the cavity and substantially covers the uppersloped portions of the die pad and the plurality of leads, and the lowersloped portions of the die pad and the plurality of leads at leastpartially extend outwardly from a lower surface of the package body. 2.The semiconductor package of claim 1, wherein the continuous, curvedsurface is substantially parabolic.
 3. The semiconductor package ofclaim 1, wherein the peripheral region of the die pad includes a groundsegment to which the first semiconductor chip is electrically coupled.4. The semiconductor package of claim 1, wherein a standoff distance bywhich at least one of the plurality of leads extends outwardly from thelower surface of the package body is substantially in the range from0.025 millimeters to 0.0625 millimeters.
 5. The semiconductor package ofclaim 1, wherein the die pad includes a lower surface, the peripheralregion includes an upper surface, a distance between the upper surfaceof the peripheral region and the lower surface of the die padcorresponds to a thickness of the die pad, and a standoff distance bywhich the die pad extends outwardly from the lower surface of thepackage body is between twenty percent and fifty percent of thethickness of the die pad.
 6. The semiconductor package of claim 1,further comprising: a first metal coating disposed on upper surfaces ofthe peripheral region and the plurality of leads; and a second metalcoating disposed on lower surfaces of the die pad and the plurality ofleads.
 7. The semiconductor package of claim 1, wherein a distance froma side surface of the package body to a side surface of any one of theplurality of leads has a minimum value of at least 0.1 millimeters. 8.The semiconductor package of claim 1, wherein a depth of the diemounting region relative to an upper surface of the peripheral region isbetween fifty-five and eighty percent of a depth of the recess relativeto the upper surface of the peripheral region.
 9. The semiconductorpackage of claim 1, wherein the plurality of leads are disposed in atleast three rows on at least one side of the die pad.
 10. Thesemiconductor package of claim 1, further comprising a protective layersubstantially covering the lower sloped portion of at least one of theplurality of leads.
 11. The semiconductor package of claim 1, furthercomprising a power segment that is spaced apart from the die pad withoutcircumscribing the die pad.
 12. The semiconductor package of claim 1,wherein the continuous, curved surface is substantially concave.
 13. Thesemiconductor package of claim 1, further comprising an attachment layerand a second semiconductor chip coupled to an upper surface of the firstsemiconductor chip by the attachment layer, wherein the package body isformed over the second semiconductor chip, and wherein the attachmentlayer includes an adhesive layer.
 14. The semiconductor package of claim1, further comprising an attachment layer and a second semiconductorchip coupled to an upper surface of the first semiconductor chip by theattachment layer, wherein the second semiconductor chip extends beyond aperipheral edge of the first semiconductor chip.
 15. The semiconductorpackage of claim 3, wherein the peripheral region of the die pad furtherincludes a power segment to which the first semiconductor chip iselectrically coupled, wherein the power segment is physically separatedfrom the ground segment.
 16. The semiconductor package of claim 6,wherein at least one of the first metal coating and the second metalcoating includes a first layer of nickel and a second layer of a metalselected from the group consisting of gold and palladium.
 17. Thesemiconductor package of claim 14, wherein the attachment layer includesa film-on-wire adhesive layer.
 18. The semiconductor package of claim14, wherein the attachment layer includes a spacer and an adhesivelayer.
 19. The semiconductor package of claim 11, wherein the powersegment has a length greater than a distance between two adjacent leadsincluded in the plurality of leads.
 20. A semiconductor packagecomprising: a die pad including: a die mounting region; a peripheralregion circumscribing a cavity with a cavity bottom, the peripheralregion including a sloped exterior facing portion and a sloped interiorfacing portion, wherein: the cavity bottom includes the die mountingregion and a recess contiguously circumscribing the die mounting region;the recess is formed at a junction of the sloped interior facing portionand the die mounting region such that a surface of the sloped interiorfacing portion and a surface of the recess correspond to a continuous,curved surface; and the sloped exterior facing portion includes an uppersloped portion, a lower sloped portion, and an apex at a junction of theupper sloped portion and the lower sloped portion; a plurality of leadsdisposed around the die pad, wherein each of the plurality of leadsincludes an upper sloped portion and a lower sloped portion; and apackage body formed over the plurality of leads so that the package bodysubstantially fills the cavity and substantially covers the upper slopedportions of the die pad and the plurality of leads, and the lower slopedportions of the die pad and the plurality of leads at least partiallyextend outwardly from a lower surface of the package body; wherein adistance from a side surface of the package body to a side surface ofany one of the plurality of leads has a minimum value substantially inthe range from 0.1 millimeters to 0.3 millimeters.
 21. A semiconductorpackage comprising: a die pad including: a base including a lowersurface that is a planar surface; a protrusion extending upwardly fromthe base, wherein the protrusion includes an upper surface; a first sidesurface extending between the upper surface of the protrusion and thelower surface of the base, wherein the first side surface includes afirst peak located closer to the lower surface of the base than to theupper surface of the protrusion; and a curved recess formed at ajunction of the base and the protrusion; a plurality of leads disposedaround the die pad, at least one of the plurality of leads including asecond side surface including a second peak; a first semiconductor chipdisposed on the upper surface of the base and electrically coupled tothe plurality of leads, wherein an upper surface of the firstsemiconductor chip is above the upper surface of the protrusion; and apackage body formed over the first semiconductor chip and the pluralityof leads so that the package body substantially covers at least aportion of the first side surface above the first peak and at least aportion of the second side surface above the second peak, and so that atleast a portion of the first side surface below the first peak and atleast a portion of the second side surface below the second peakprotrude from a lower surface of the package body.
 22. The semiconductorpackage of claim 21, wherein a standoff distance by which at least oneof the plurality of leads extends outwardly from the lower surface ofthe package body is between twenty percent and fifty percent of athickness of the at least one of the plurality of leads.
 23. Thesemiconductor package of claim 21, wherein a standoff distance by whichthe die pad extends outwardly from the lower surface of the package bodyis substantially in the range from 0.025 millimeters to 0.0625millimeters.
 24. The semiconductor package of claim 21, wherein an uppersurface of the base includes: a central region on which the firstsemiconductor chip is disposed; and a recess around the central region.25. The semiconductor package of claim 21, further comprising anattachment layer and a second semiconductor chip coupled to an uppersurface of the first semiconductor chip by the attachment layer, whereinthe second semiconductor chip extends beyond a peripheral edge of thefirst semiconductor chip.
 26. The semiconductor package of claim 21,wherein the first peak is substantially level with the second peak. 27.The semiconductor package of claim 21, wherein a thickness of theprotrusion is greater than a thickness of the base.
 28. Thesemiconductor package of claim 21, further comprising a protective layersubstantially covering the first side surface below the first peak of atleast one of the plurality of leads.
 29. The semiconductor package ofclaim 21, further comprising a power segment that is electricallyisolated from the die pad, the power segment disposed between the diepad and one or more of the plurality of leads.
 30. The semiconductorpackage of claim 24, wherein the central region defines a plane, andwherein the first peak is disposed below the plane.
 31. Thesemiconductor package of claim 30, wherein the upper surface of theprotrusion is disposed substantially in the range from 0.05 to 0.08millimeters above the plane.
 32. A semiconductor package, comprising: adie pad comprising: a lower surface that is a planar surface and thatextends to a peripheral edge of the die pad; a die mounting region; aperipheral region circumscribing the die mounting region such that athickness of the peripheral region is greater than a thickness of thedie mounting region, wherein the peripheral region further comprises acurved inner surface facing toward the die mounting region; and a curvedrecess formed between the curved inner surface and the die mountingregion and extending below an upper surface of the die mounting region.33. The semiconductor package of claim 32, wherein the peripheral regionfurther comprises: an upper region which is substantially horizontal,the upper region being dimensioned to permit wirebonding.
 34. Thesemiconductor package of claim 32, wherein the peripheral region furthercomprises: an outer surface, the outer surface comprising: an upperregion having a concave profile; a lower region adjacent to the upperregion and having a concave profile; and a peak formed at a junction ofthe upper region and the lower region.
 35. The semiconductor package ofclaim 34, further comprising: a package body, wherein the package bodyphysically contacts the upper region, but does not physically contactthe lower region.
 36. The semiconductor package of claim 34, furthercomprising: a package body, wherein the package body covers the upperregion, and wherein the lower region extends outwardly from a lowersurface of the package body.
 37. The semiconductor package of claim 33,wherein the upper region further comprises a plating layer.